Digi NS9750 - Manual (Page 895)

I - I n d e x - 2 5
780
FIFO Interrupt Status 0 register
771
FIFO Interrupt Status 1 register
771
FIFO Interrupt Status 2 register 773
FIFO Interrupt Status 3 register 775
FIFO Interrupt Status registers 769 -
775
FIFO Packet Control registers 780
FIFO Status and Control registers 781
Global Interrupt Enable register 720
Global Interrupt Status register 721
HcBulkCurrentED register 744
HcBulkHeadED register
743
HcCommandStatus register 730
HcControl register 727
HcControlCurrentED register 742
HcControlHeadED register 741
HcDoneHead register 746
HcFmInterval register
747
HcFmNumber register 749
HcFmRemaining register 748
HcHCCA register 739
HcInterruptDisable register 737
HcInterruptEnable register
735
HcInterruptStatus register
733
HcLsThreshold register 751
HcPeriodCurrentED register 740
HcPeriodicStart register 750
HCRevision register 726
HcRhDescriptorA register
753
HcRhDescriptorB register 755
HcRhPortStatus1 register 759
HcRhStatus register 756
host block 712 - 714
module architecture 708
port features
4
register "block" addresses 716
registers 716 - 783
device block 765 - 767
device block addresses
765
Device Endpoint FIFO Control and
Data register
addresses
767
Device Endpoint FIFO Control and
Data registers 767 - 783
global 716 - 725
Global Control and Status 717
global register addresses 716
host block 725 - 764
host block addresses
725
host block reserved bits 725
host block, root hub partition
registers 752
root hub 752
transmission error handling
714
USB timing diagrams 832 - 834
USB interface pinout 43
USB timing 832 - 834
V
vector interrupt controller
6
vectored interrupt controller (VIC)
270
vertical axis panel 582
vertical compare interrupt
(VCOMPINTR) 598
W
wait state generation
123
water level marks 568
WRAP bit 476 , 505
WRAP bit, Ethernet 326 , 327
write protection
dynamic memory controller
162
static memory controller 122