Lcdstatus register, Register bit assignment – Digi NS9750 User Manual
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L C D C o n t r o l l e r
LCDStatus register
Address: A080 0020
The LCDStatus register provides raw interrupt status.
On a read, the register returns three bits that can generate interrupts when
set.
On writes to the register, a bit value of 1 clears the interrupt corresponding
to that bit. Writing a 0 has no effect.
Note:
R/C indicates an access of read or clear.
Register bit assignment
Bits
Access
Mnemonic
Reset
Description
D31:05
N/A
Reserved
N/A
N/A
D04
R/C
MBERROR
0x0
AHB master bus error status
Set when the AHB master encounters a bus error
response from a slave.
D03
R/C
VCOMP
0x0
Vertical compare
Set when one of the four vertical regions, selected by
the LCDControl register, is reached. (See LcdVcomp
in "LCDControl register" on page 590).
D02
R/C
LNBU
0x0
LCD next address base update
This bit is mode-dependent, and is set when the
current base address registers have been updated
successfully by the next address registers.
Signifies that a new next address can be loaded if
double buffering is in use.
D01:00
N/A
Reserved
0x0
N/A
Table 359: LCDStatus register
MB
ERROR
VCOMP
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
Reserved
LNBU