Digi NS9750 - Manual (Page 7)

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TLB structure ....................................................................104
Caches and write buffer ..............................................................105
Cache features ..................................................................105
Write buffer .....................................................................106
Enabling the caches ............................................................107
Cache MVA and Set/Way formats ............................................109
Noncachable instruction fetches ....................................................111
Self-modifying code ............................................................112
AHB behavior ....................................................................112
Instruction Memory Barrier...........................................................113
IMB operation....................................................................113
Sample IMB sequences .........................................................114
C h a p t e r 4 : S y s t e m C o n t r o l M o d u l e ................................................................. 115
System Control Module features ....................................................116
Bus interconnection ...................................................................116
System bus arbiter.....................................................................116
Arbiter configuration examples ..............................................120
Address decoding ......................................................................123
Programmable timers .................................................................125
Software watchdog timer......................................................125
General purpose timers/counters ............................................125
Interrupt controller ...................................................................129
Vectored interrupt controller (VIC) flow....................................132
System attributes......................................................................133
PLL configuration ...............................................................133
Bootstrap initialization ........................................................134
System configuration registers ......................................................138
AHB Arbiter Gen Configuration register .....................................144
BRC0, BRC1, BRC2, and BRC3 registers......................................145
Timer 0–15 Reload Count registers...........................................146
Timer 0–15 Read register ......................................................147
Interrupt Vector Address Register Level 0–31 ..............................147
Int (Interrupt) Config (Configuration) registers (0–31) ....................148
ISRADDR register ................................................................150
Interrupt Status Active.........................................................151