Digi NS9750 - Manual (Page 256)

R e g i s t e r s
2 3 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
D07 R/W PB Byte lane state
0 For reads, all bits in byte_lane_sel_n[3:0] are high.
For writes, the respective active bits in byte_lane_sel_n[3:0] are
low (reset value for chip select 0, 2, and 3 on reset_n ).
1 For reads, the respective active bits in byte_lane_sel_n[3:0] are
low.
For writes, the respective active bits in byte_lane_sel_n[3:0] are
low.
Note: Setting this bit to 0 disables the write enable signal. WE_n
will always be set to 1 (that is, you must use byte lane
select signals).
The value of the chip select 1 byte lane state field on power-on reset
(
reset_n ) is determined by the boot_strap[0] signal. This value can be
overridden by software. This field is not affected by AHB reset
(
HRESETn ).
The byte lane state bit (PB) enables different types of memory to be
connected. For byte-wide static memories, the
byte_lane_sel_n[3:0]
signal from the memory controller is usually connected to WE_n
(write enable). In this case, for reads, all byte_lane_sel_n[3:0] bits
must be high, which means that the byte lane state bit must be low.
16-bit wide static memory devices usually have the
byte_lane_sel_n[3:0] signals connected to the nUB and nLB (upper
byte and lower byte) signals in the static memory. In this case, a
write to a particular byte must assert the appropriate
nUB or nLB
signal low. For reads, all nUB and nLB signals must be asserted low
so the bus is driven. In this case, the byte lane state must be high.
Note: For chip select 1, the value of the boot-strap[0] signal is
reflected in this field. When programmed, this register
reflects the last value written into it.
D06 R/W PC Chip select polarity
0 Active low chip select
1 Active high chip select
The value of the chip select polarity on power-on reset ( reset_n ) for
chip select 1 is determined by the gpio[49] signal. This value can be
overridden by software. This field is not affected by AHB reset
(
HRESETn ).
D05:04 N/A Reserved N/A (do not modify)
Bits Access Mnemonic Description
Table 159: Static Memory Configuration 0–3 registers