Digi NS9750 - Manual (Page 484)

P C I s y s t e m c o n f i g u r a t i o n s
4 6 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
When the
PCI_CENTRAL_RSC_n
pin is pulled high (see Figure 73), these functions
operate differently:
RST#
is configured as an input, and must be supplied by the system. In this
situation,
RST#
is used as another system reset to NS9750; that is, either
reset_n
or
RST#
can reset NS9750, and both must be negated to take NS9750
out of reset.
SERR#
is configured as output.
AD[31:0]
,
C/BE[3:0]
, and
PAR
are tri-stated when
RST#
is asserted.
The system must provide pullup resistors on the following signals, regardless of the
state of
PCI_CENTRAL_RSC_n
:
FRAME#
TRDY#
IRDY#
DEVSEL#
STOP#
SERR#
PERR#
LOCK#
Note: The NS9750 does not have a
LOCK#
pin associated with it. If any PCI
device in the system uses the
LOCK#
signal, the signal must have a pullup
resistor.
INTA#
INTB#
INTC#
INTD#
All
REQ#
inputs to NS9750
All
GNT#
outputs from NS9750 that are connected to other PCI devices in the
system (because they are tri-stated during
RST#
)
The PCI clock can be either generated from NS9750 (see Figure 72, "System
connections to NS9750 — Internal arbiter and central resources," on page 456) or
provided by an external source (see Figure 73, "System connections to NS9750 —
External arbiter and central resources," on page 457). The PCI
CLK
input pad has a
weak internal pullup.