Sdram refresh mode, Clock enable timing, Figure 111: sdram refresh mode timing – Digi NS9750 User Manual
Page 827: Figure 112: clock enable timing
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w w w . d i g i e m b e d d e d . c o m
8 0 3
T i m i n g
SDRAM refresh mode
Figure 111: SDRAM refresh mode timing
Clock enable timing
Figure 112: Clock enable timing
prechg
CS0 rf
CS1 rf
CS2 rf
CS3 rf
M9
M8
M7
M6
M6
M6
M6
clk_out<3:0>
dy_cs0_n
dy_cs1_n
dy_cs2_n
dy_cs3_n
ras_n
cas_n
we_n
M13
M14
M3
clk_enable.td
clk_out<3:0>
clk_en<3:0>
SDRAM cycle
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