Digi NS9750 - Manual (Page 125)

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W o r k i n g w i t h t h e C P U
Alignment faults
If alignment fault checking is enabled (the A bit in the R1: Control register is set; see
"R1: Control register," beginning on page 58), the MMU generates an alignment fault
on any data word access if the address is not word-aligned, or on any halfword access
if the address is not halfword-aligned — irrespective of whether the MMU is enabled.
An alignment fault is not generated on any instruction fetch or byte access.
Note:
If an access generates an alignment fault, the access sequence aborts
without reference to other permission checks.
Translation faults
There are two types of translation fault: section and page.
A section translation fault is generated if the level one descriptor is marked
as invalid. This happens if bits [1:0] of the descriptor are both 0.
A page translation fault is generated if the level one descriptor is marked as
invalid. This happens if bits [1:0] of the descriptor are both 0.
Domain faults
There are two types of domain faults: section and page.
Section: The level one descriptor holds the four-bit domain field, which
selects one of the 16 two-bit domains in the Domain Access Control register.
The two bits of the specified domain are then checked for access
permissions as described in Table 42: "Interpreting access permission (AP)
bits" on page 98. The domain is checked when the level one descriptor is
returned.
Page: The level one descriptor holds the four-bit domain field, which
selects one of the 16 two-bit domains in the Domain Access Control register.
The two bits of the specified domain are then checked for access
permissions as described in Table 42: "Interpreting access permission (AP)
bits" on page 98. The domain is checked when the level one descriptor is
returned.
If the specified access is either no access (00) or reserved (10), either a section
domain fault or a page domain fault occurs.