Digi NS9750 User Manual
Page 356
E t h e r n e t f r o n t - e n d m o d u l e
3 3 2
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
The status bits for all interrupts are available in the Ethernet Interrupt Status
register, and the associated enables are available in the Ethernet Interrupt Enable
register. Each interrupt status bit is cleared by writing a 1 to it.
Resets
Table 204 provides a summary of all resets used for the Ethernet front-end and MAC,
as well as the modules the resets control.
Transmit buffer not ready
F bit not set in transmit buffer descriptor when read from TX
buffer descriptor RAM, for a frame in progress.
TX
Transmit complete
Frame transmission complete.
TX
TXERR
Frame not transmitted successfully.
TX
TXIDLE
TX_WR
logic in idle mode because there are no frames to send.
TX
Interrupt condition
Description
Interrupt
Table 203: Ethernet interrupt conditions
Bit field
Register
Active
state
Default
state
Modules reset
ERX
Ethernet General Control
Register #1
0
0
RX_RD, RX_WR
ETX
Ethernet General Control
Register #1
0
0
TX_RD, TX_WR
MAC_HRST
Ethernet General Control
Register #1
1
0
MAC, STAT, RMII, RX_WR,
TX_RD, programmable registers in
Station Address Logic
SRST
MAC1
1
1
MAC (except programmable
registers), Station Address Logic
(except programmable registers),
RMII, RX_WR, TX_RD
RPERFUN
MAC1
1
0
MAC RX logic
RPEMCST
MAC1
1
0
MAC PEMCS (TX side)
RPETFUN
MAC1
1
0
MAC TX logic
Table 204: Reset control