Digi NS9750 - Manual (Page 362)

E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s
3 3 8 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
A060 0448 SA3 Station Address register #3
A060 0500 SAFR Station Address Filter register
A060 0504 HT1 Hash Table Register #1
A060 0508 HT2 Hash Table Register #2
A060 0680 STAT Statistics Register Base (45 registers)
A060 0A00 RXAPTR RX_A Buffer Descriptor Pointer register
A060 0A04 RXBPTR RX_B Buffer Descriptor Pointer register
A060 0A08 RXCPTR RX_C Buffer Descriptor Pointer register
A060 0A0C RXDPTR RX_D Buffer Descriptor Pointer register
A060 0A10 EINTR Ethernet Interrupt Status register
A060 0A14 EINTREN Ethernet Interrupt Enable register
A060 0A18 TXPTR TX Buffer Descriptor Pointer register
A060 0A1C TXRPTR TX Recover Buffer Descriptor Pointer register
A060 0A20 TXERBD TX Error Buffer Descriptor Pointer register
A060 0A24 Reserved
A060 0A28 RXAOFF RX_A Buffer Descriptor Pointer Offset register
A060 0A2C RXBOFF RX_B Buffer Descriptor Pointer Offset register
A060 0A30 RXCOFF RX_C Buffer Descriptor Pointer Offset register
A060 0A34 RXDOFF RX_D Buffer Descriptor Pointer Offset register
A060 0A38 TXOFF Transmit Buffer Descriptor Pointer Offset register
A060 0A3C RXFREE RX Free Buffer register
A060 1000 TXBD TX Buffer Descriptor RAM (256 locations)
Address Register Description
Table 205: Ethernet Control and Status register map