Digi NS9750 - Manual (Page 737)

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U S B C o n t r o l l e r M o d u l e
Figure 103: USB host architecture
Packet data flow
The host block initiates all transfers on the USB. Data travels through a four-word
FIFO in either direction. The Serial Interface Engine (SIE) performs the tasks required
to receive and send packets on the USB.
The host block is the master of the USB. At the highest level, the host maintains a
database of the existing network topology, and can reconfigure any associated
device.
At the next level, there are four linked lists of endpoint descriptors, each tied to one
or more transfer descriptors. The four lists correspond to the four endpoint types
that are accessed in a specified priority. The host begins processing these lists each
millisecond, after sending the SOF packet. When a given endpoint descriptor is
processed, the host generates a packet to move data and the transfer descriptor(s)
defines the source or destination of the data in system memory. Interrupts generally
are generated as each transfer descriptor is retired.
The core is connected with a master interface on the BBus to move incoming or
outgoing data to system memory. Based on expected timing of four microseconds for
bus turnaround, the four-word FIFOs included in the core prevent underrun and/or
overrun occurrences. Bursting is supported to minimize the bus bandwidth that is
text
OHCI
Regs
FIFO
FIFO
BBUS
Slave IF
Master IF
SIE
To XCVR From XCVR