Digi NS9750 - Manual (Page 9)

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Dynamic memory controller .........................................................224
Write protection ................................................................224
Access sequencing and memory width ......................................224
Address mapping ................................................................225
Registers ................................................................................264
Register map ....................................................................264
Reset values .....................................................................266
Control register .................................................................267
Status register...................................................................269
Configuration register..........................................................269
Dynamic Memory Control register............................................270
Dynamic Memory Refresh Timer register ...................................272
Dynamic Memory Read Configuration register .............................274
Dynamic Memory Precharge Command Period register ...................275
Dynamic Memory Active to Precharge Command Period register .......276
Dynamic Memory Self-refresh Exit Time register ..........................277
Dynamic Memory Last Data Out to Active Time register .................278
Dynamic Memory Data-in to Active Command Time register ............279
Dynamic Memory Write Recovery Time register ...........................280
Dynamic Memory Active to Active Command Period register............281
Dynamic Memory Auto Refresh Period register ............................282
Dynamic Memory Exit Self-refresh register .................................283
Dynamic Memory Active Bank A to Active Bank B Time register ........284
Dynamic Memory Load Mode register to Active Command Time register ..
285
Static Memory Extended Wait register ......................................286
Dynamic Memory Configuration 0–3 registers ..............................287
Dynamic Memory RAS and CAS Delay 0–3 registers ........................291
Static Memory Configuration 0–3 registers..................................292
Static Memory Write Enable Delay 0–3 registers ...........................296
Static Memory Output Enable Delay 0–3 registers .........................297
Static Memory Read Delay 0–3 registers.....................................298
Static Memory Page Mode Read Delay 0–3 registers.......................299
Static Memory Write Delay 0–3 registers ....................................300
Static Memory Turn Round Delay 0–3 registers.............................301
C h a p t e r 6 : E t h e r n e t C o m m u n i c a t i o n M o d u l e ...................................... 315