Digi NS9750 - Manual (Page 504)

T w o - c h a n n e l A H B D M A c o n t r o l l e r ( A H B b u s )
4 8 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Design Limitations
The AHB DMA logic contains several design limitations. Carefully consider these
limitations when making system level implementation decisions:
The AHB DMA control logic is designed to operate on four-byte quantities,
which limits the minimum number of accesses that the memory controller
can perform on narrow external peripherals. Accesses to an 8-bit peripheral
will always occur in multiples of four. Accesses to a 16-bit peripheral will
always occur in multiples of two. Asserting the REQ signal when the
peripheral is unable to meet the above conditions results in unpredictable
system behavior.
The length field in the buffer descriptor must be set to a value equal to the
burst length multiplied by four. The burst length is specified in the SB/DB
field in the DMA Channel 1/2 Control register.
The peripheral can assert the REQ signal no more often than the AHB DMA
response latency for the given system (see "Calculating AHB DMA response
latency" on page 480).
The REQ signal is an asynchronous input to the NS9750. For a REQ signal
assertion to be found by the control logic, it must be asserted for no less
than 4 AHB clock cycles and no more than 20 AHB clock cycles.
The AHB DMA channels are allocated the unused BBus peripheral bandwidth,
which limits the bandwidth available to the AHB DMA channels. Minimum
bandwidth requirements can be met by allocating more AHB bus timeslots
to the BBus master using the BRC registers in the System Control module.
The AHB DMA channels provide no latency guarantee because they do not
directly attach to the AHB bus. Allocating more system bandwidth reduces
the worst case latency. In a fully loaded system, the response to the REQ
signal assertion can be as long as 83us.
Calculating AHB DMA response latency
AHB DMA controller latency is defined as the time between the assertion of the
peripheral’s REQ signal and the AHB DMA channel being granted access to the AHB
bus. Response latency is a function of the number of AHB timeslots given to the BBus
and the number of BBus peripherals in use. Note that the BBus peripherals