Digi NS9750 - Manual (Page 670)

S P I m o d e
6 4 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
SPI mode
The NS9750 ASIC SPI controller provides these key features:
Four-wire interface (
DATA_OUT, DATA_IN, CLK, ENABLE
)
Master or slave configuration
Programmable MSB/LSB formatting
Programmable
ENABLE
polarity
Programmable SPI mode (0, 1, 2, 3)
The SPI controller provides a full-duplex, synchronous, character-oriented data
channel between master and slave devices, using a four-wire interface (
DATA_OUT,
DATA_IN, CLK, ENABLE
). The master interface operates in a broadcast mode. The slave
interface is activated using the
ENABLE
signal. You can configure the master interface
to address various slave interfaces using GPIO pins.
The transmitter and receiver use the same clock. When configured in master mode,
the channel’s bit-rate generator (see "Bit-rate generator" on page 645) provides the
timing reference.
SPI is useful for providing simple parallel/serial data conversion to stream serial data
between memory and a peripheral. The SPI port has no protocol associated with it
other than that it transfers information in multiples of 8 bits.
The SPI port simultaneously is capable of full duplex operation. The transfer of
information is controlled by a single clock signal.
For the SPI master interface, the clock signal is an output.
For the SPI slave interface, the clock signal is an input.
The
ENABLE
signal also qualifies the transfer of information. The SPI
ENABLE
signal
must be active for data transfers to occur, regardless of the SPI clock signal.
SPI modes
The four SPI modes are distinguished by the polarity in which the SPI
CLK
idles and
the SPI
CLK
data phase used to capture SPI
DATA_IN
and drive SPI
DATA_OUT
. Table 381
describes the four modes and the register settings used to select the modes.