Digi NS9750 - Manual (Page 632)

S e r i a l p o r t p e r f o r m a n c e
6 0 8 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
To facilitate an interrupt when either the RRDY or RBC status bits are active, the
processor must set one or both of the corresponding interrupt enables in Serial
Channel B/A/C/D Control Register A.
Using the DMA controller
When using DMA, the processor need not interface with any of the serial port
registers for data flow; rather, the processor must interface with the DMA channel
registers and the DMA buffer descriptor block. To facilitate use of transmit DMA, the
ERXDMA field in Serial Channel B/A/C/D Control register A must be set active high.
When ERXDMA is set active high, disable the serial receiver interrupts.
Serial port performance
The serial ports have a finite performance limit on their ability to handle various
serial protocols. The performance is limited by the speed of the SYSCLK operating the
NS9750 ASIC. The configured speed for the internal PLL defines the BCLK rate; for
UART (x8), the serial port maximum rate is 1834200 baud, for UART (x16), the serial
port maximum rate is 921600 baud, and for UART (x32), the serial port maximum rate
is 460800 baud.
Serial port control and status registers
The configuration registers for serial controller B are located at
0x9020_0000
; the
configuration registers for serial controller A are located at
0x9020_0040
. Table 365
shows a single, two-channel address map for serial controllers B and A.
All configuration registers must be accessed as 32-bit words and as single accesses
only. Bursting is not allowed.
Address Description
9020 0000 Channel B Control Register A
9020 0004 Channel B Control Register B
Table 365: Serial channel B & A configuration registers