Back-to-back inter-packet-gap register, Register bit assignment, Table 213: back-to-back inter-packet-gap register – Digi NS9750 User Manual
Page 378
E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s
3 5 4
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Back-to-Back Inter-Packet-Gap register
Address: A060 0408
Register bit assignment
Bits
Access
Mnemonic
Reset
Description
D31:07
N/A
Reserved
N/A
N/A
D06:00
R/W
IPGT
0x00
Back-to-back inter-packet-gap
Programmable field that indicates the nibble time offset
of the minimum period between the end of any
transmitted frame to the beginning of the next frame.
Full-duplex mode
Register value should be the appropriate period in
nibble times minus 3.
Recommended setting is
0x15 (21d)
, which
represents the minimum IPG of 0.96 uS (in 100
Mbps) or 9.6uS (in 10 Mbps).
Half-duplex mode
Register value should be the appropriate period in
nibble times minus 6.
Recommended setting is
0x12 (18d)
, which
represents the minimum IPG of 0.96 uS (in 100
Mbps) or 9.6 uS (in 10 Mbps).
Table 213: Back-to-Back Inter-Packet-Gap register
Reserved
IPGT
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved