Digi NS9750 - Manual (Page 370)

E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s
3 4 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
D10 R TXAEC 0x0 TX abort — excessive collisions
When set, indicates that the frame was aborted because
the number of collisions exceeded the value set in the
Collision Window/Retry register. If this bit is set, the
TX_WR logic stops processing frames and sets the
TXERR bit in the Ethernet Interrupt Status register.
D09 R TXAUR 0x0 TX abort — underrun
When set, indicates that the frame was aborted because
the TX_FIFO had an underrun. If this bit is set, the
TX_WR logic stops processing frames and sets the
TXERR bit in the Ethernet Interrupt Status register.
D08 R TXAJ 0x0 TX abort — jumbo
When set, indicates that the frame’s length exceeded the
value set in the Maximum Frame register (see
page 357). TXAJ is set only if the HUGE bit in MAC
Configuration Register #2 (see page 351) is set to 0.
Jumbo frames result in the TX buffer descriptor buffer
length field (see "Buffer length" on page 327) being set
to 0x000.
If the HUGE bit is set to 0, the frame is truncated. If
TXAJ is set, the
TX_WR logic stops processing frames
and sets the TXERR bit in the Ethernet Interrupt Status
register.
D07 R Not used 0x0 Always set to 0.
D06 R TXDEF 0x0 Transmit frame deferred
When set, indicates that the frame was deferred for at
least one attempt, but less than the maximum number
for an excessive deferral. TXDEF is also set when a
frame was deferred due to a collision.
This bit is not set for late collisions.
D05 R TXCRC 0x0 Transmit CRC error
When set, indicates that the attached CRC in the frame
did not match the internally-generated CRC. This bit is
not set if the MAC is inserting the CRC in the frame
(that is, the CRCEN bit is set in MAC Configuration
Register #2). If TXCRC is set, the
TX_WR logic stops
processing frames and sets the TXERR bit in the
Ethernet Interrupt Status register.
Bits Access Mnemonic Reset Description
Table 209: Ethernet Transmit Status register