Digi NS9750 - Manual (Page 609)

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L C D C o n t r o l l e r
D13 R/W IPC 0x0 Invert panel clock
0 Data changes on the rising edge of CLCP.
1 Data changes on the falling edge of CLCP
Controls the phasing of the LCD data relative to the
LCD clock (
CLCP ). The NS9750 changes the data on
the opposite edge of the clock used to capture the data.
D12 R/W IHS 0x0 Invert horizontal synchronization
0 CLLP pin is active high and inactive low
1 CLLP pin is active low and inactive high
Inverts the polarity of the CLLP signal.
D11 R/W IVS 0x0 Invert vertical synchronization
0 CLFP pin is active high and inactive low
1 CLFP pin is active low and inactive high
Inverts the polarity of the CLFP signal.
D10:06 R/W ACB 0x00 AC bias pin frequency
Applies only to STN displays, which require the pixel
voltage polarity to be reversed periodically to prevent
damage due to DC charge accumulation. Program this
field with the required value minus one, to apply the
number of line clocks between each toggle of the AC
bias pin (
CLAC ).
This field has no effect when the LCD controller is
using TFT mode, which uses the
CLAC pin as a data
enable signal.
D05 N/A Reserved N/A N/A
Bits Access Mnemonic Reset Description
Table 353: LCDTiming2 register