Digi NS9750 - Manual (Page 120)

M e m o r y M a n a g e m e n t U n i t ( M M U )
9 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
The access control mechanisms of the MMU detect the conditions that produce these
faults. If a fault is detected as a result of a memory access, the MMU aborts the
access and signals the fault condition to the CPU core. The MMU retains status and
address information about faults generated by the data accesses in the Data Fault
Status register and Fault Address register (see "Fault Address and Fault Status
registers" on page 96).
The MMU also retains status about faults generated by instruction fetches in the
Instruction Fault Status register.
An access violation for a given memory access inhibits any corresponding external
access to the AHB interface, with an abort returned to the CPU core.
Fault Address and Fault Status registers
On a data abort, the MMU places an encoded four-bit value — the fault status — along
with the four-bit encoded domain number in the Data Fault Status register. Similarly,
on a prefetch abort, the MMU places an encoded four-bit value along with the four-
bit encoded domain number in the Instruction Fault Status register. In addition, the
MVA associated with the data abort is latched into the Fault Address register. If an
access violation simultaneously generates more than one source of abort, the aborts
are encoded in the priority stated in Table 39. The Fault Address register is not
updated by faults caused by instruction prefetches.
Priority Source Size Status Domain
Highest Alignment --- 0b00x1 Invalid
External abort on transmission First level
Second level
0b1100
0b1110
Invalid
Valid
Translation Section page 0b0101
0b0111
Invalid
Valid
Domain Section page 0b1001
0b1011
Valid
Valid
Permission Section page 0b1101
0b1111
Valid
Valid
Lowest External abort Section page 0b1000
0b1010
Valid
Valid
Table 39: Priority encoding of fault status