Digi NS9750 - Manual (Page 650)

S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s
6 2 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
D25:24 R/W CLKMUX 00 Bit-rate generator clock source
Controls the bit-rate generator clock source. The bit-rate
generator can be configured to use one of four clock
sources:
00 x1_sys_osc/M (see Table 364, “Bit-rate generation
clock sources,” on page 604 for more information).
This is the recommended setting for standard
UART baud rate generation. This selection is not
valid when the PLLBP field in the PLL
Configuration register is set to 1.
01 BCLK
This is the recommended setting for SPI operation.
10 Input clock defined by external receive clock on
GPIO pins gpio[6], gpio[14], gpio[22], and
gpio[26] for serial ports B, A, C, and D,
respectively.
11 Input clock defined by external transmit clock on
GPIO pins gpio[7], gpio[15], gpio[23], and
gpio[27] for serial ports B, A, C, and D,
respectively.
D23 R/W TXCINV 0 Transmit clock invert
Controls the relationship between transmit clock and
transmit data:
When set to 0, transmit data changes relative to the
falling edge transition of the transmit clock.
When set to 1, transmit data changes relative to the
rising edge transition of the transmit clock.
D22 R/W RXCINV 0 Receive clock invert
Controls the relationship between receive clock and
receive data:
When set to 0, the receive data input is sampled at
the rising edge transition of the receive clock.
When set to 1, the receive data input is sampled at
the falling edge transition of the receive clock.
D21 N/A Reserved N/A N/A
Bits Access Mnemonic Reset Description
Table 370: Serial Channel B/A/C/D Bit-rate register