Dma control register – Digi NS9750 User Manual
Page 538
D M A C o n t r o l a n d S t a t u s r e g i s t e r s
5 1 4
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
DMA Control register
Address: DMA1
9000 0010 / 0030 / 0050 / 0070 / 0090 / 00B0 / 00D0 / 00F0 / 0110 / 0130 /
0150 / 0170 / 0190 / 01B0 / 01D0 / 01F0
Address: DMA2
9011 0010 / 0030 / 0050 / 0070 / 0090 / 00B0 / 00D0 / 00F0 / 0110 / 0130 /
0150 / 0170 / 0190 / 01B0 / 01D0 / 01F0
The DMA Control register contains required transfer control information. There is a
DMA Control register for each channel within each DMA controller module.
Register bit assignment
Bits
Access
Mnemonic
Reset
Description
D31
R/W
CE
0
Channel enable
0
Disables DMA operations
1
Enables DMA operations
Enables and disables DMA operations, as wanted.
D30
R/W
CA
0
Channel abort
When set, causes the current DMA operation to complete
and closes the buffer.
D29:28
R/W
BB
0
Bus bandwidth
Always set to 0.
Table 313: BBus DMA Control register bit definition
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
STATE
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
BB
Not used
REQ
BDR
CE
CA
SIZE
INDEX
MODE
BTE
SINC_N