Digi NS9750 - Manual (Page 30)

N S 9 7 5 0 F e a t u r e s
6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Each DMA channel supports memory-to-memory transfers
Power management (patent pending)
Power save during normal operation
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Disables unused modules
Power save during sleep mode
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Sets memory controller to refresh
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Disables all modules except selected wakeup modules
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Wakeup on valid packets or characters
Vector interrupt controller
Decreased bus traffic and rapid interrupt service
Hardware interrupt prioritization
General purpose timers/counters
16 independent 16-bit or 32-bit programmable timers or counters
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Each with an I/O pin
Mode selectable into:
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Internal timer mode
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External gated timer mode
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External event counter
Can be concatenated
Resolution to measure minute-range events
Source clock selectable: internal clock or external pulse event
Each can be individually enabled/disabled
System timers
Watchdog timer
System bus monitor timer
System bus arbiter timer
Peripheral bus monitor timer
General purpose I/O
50 programmable GPIO pins (muxed with other functions)
Software-readable powerup status registers for every pin for customer-
defined bootstrapping