Digi NS9750 - Manual (Page 500)

T w o - c h a n n e l A H B D M A c o n t r o l l e r ( A H B b u s )
4 7 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Descriptor list processing
When a DMA controller has completed the operation specified by the current buffer
descriptor, the controller clears the F bit and fetches the next buffer descriptor. A
DMA channel asserts the NRIP field in the DMA Status and Interrupt Enable register
(see "DMA Status and Interrupt Enable register" on page 494) and returns to the idle
state after fetching a buffer descriptor with the F bit in the incorrect state.
W The wrap bit. When set, this bit tells the DMA controller that this is the
last buffer descriptor within the continuous list of descriptors. The next
buffer descriptor is found using the initial DMA channel buffer descriptor
pointer.
When the wrap bit is not set, the next buffer descriptor is found using an
offset of 0x10 from the current buffer descriptor.
I The interrupt bit. Tells the DMA controller to issue an interrupt to the
CPU when the buffer is closed due to normal channel completion. The
interrupt occurs no matter what the normal completion interrupt enable
configuration is for the DMA channel.
L The last bit. When set, this bit tells the DMA controller that this buffer
descriptor is the last descriptor that completes an entire message frame.
The DMA controller uses this bit to assert the normal channel completion
status when the byte count reaches zero.
If this bit is set, the DMA controller remains in the IDLE state after
asserting the normal channel completion status. A write to the CE field in
the DMA Channel 1/2 Control register re-enables the DMA channel.
F The full bit. When set, this bit indicates that the buffer descriptor is valid
and can be processed by the DMA channel.
The DMA channel clears this bit after completing the transfer(s).
The DMA channel doesn’t try a transfer with the F bit clear.
The DMA channel enters an IDLE state after fetching a buffer
descriptor with the F bit cleared.
When the device driver modifies the F bit, it must also write a 1 to the
CE bit in the DMA Channel 1/2 Control register to activate the idle
channel.
Reserved Write zero to this field.
Status Not used. Read back 0x0000.
Field/Section Description
Table 289: BBus bridge DMA buffer descriptor definition