Digi NS9750 - Manual (Page 871)

Index
I - I n d e x - 1
Numerics
10/100 Ethernet MAC
3
1284 parallel peripheral port 5
16-bit byte gap counter 689 , 690
16-bit maximum buffer counter 689 , 690
16-bit Thumb instruction set 48 , 50
32-bit ARM instruction set
48
,
50
8-bit Java instruction set
50
A
absolute maximum ratings 788
access sequencing and memory width,
dynamic memory controller
162
access sequencing and memory width,
static memory controller 123
Active Interrupt Level Status register 301
address connectivity 150
address manipulation, ARM926EJ-S
51
address mapping
163
-
201
address translation, MMU 81 - 95
AHB address decoding and translation 408
AHB Arbiter Gen Configuration
register
282
AHB behavior with noncacheable
instruction fetches 112
AHB bus arbiter timeout 257
AHB bus error interrupt 409
AHB input clock, LCD 565
AHB interface, LCD 568 - 579
dual DMA FIFOs amd associated control
logic 568
external pad interface signals 575
generating interrupts 575
grayscaler
574
LCD panel signal multiplexing
details 575
master and slave interfaces 568
panel clock generator 574
pixel serializer 569
RAM palette
573
timing controller 574
upper and lower panel formatters 574
AHB master interface 405
AHB slave/target interface 406
alignment faults
101
ambient temperatures
7
arbitration and multiplexing, BBus
bridge 468
ARM boot configuration (SPI-EEPROM) 486
ARM debug architecture
48
ARM Wake-up register
541
ARM926EJ-S processor 47