Digi NS9750 - Manual (Page 202)

D y n a m i c m e m o r y c o n t r o l l e r
1 7 8 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Table 108 shows the outputs from the memory controller and the corresponding
inputs to the 64M SDRAM (8Mx8, pins 13 and 14 used as bank selects).
6 6 16 8
5 5 15 7
4 4 14 6
3 3 13 5
2 2 12 4
1 1 11 3
0 0 10 2
Output address
(
ADDROUT )
Memory device
connections AHB address to row
address AHB address to
column address
14 BA1 23 23
13 BA0 24 24
12 - - -
11 11 22 -
10 10/AP 21 AP
9 9 20 -
8 8 19 10
7 7 18 9
6 6 17 8
5 5 16 7
4 4 15 6
3 3 14 5
2 2 13 4
Table 108: Address mapping for 64M SDRAM (8Mx8, BRC)
Output address
(
ADDROUT )
Memory device
connections AHB address to row
address AHB address to
column address
Table 107: Address mapping for 64M SDRAM (4Mx16, BRC)