Digi NS9750 - Manual (Page 129)

w w w . d i g i e m b e d d e d . c o m 1 0 5
W o r k i n g w i t h t h e C P U
times. To guarantee coherency if a level one descriptor is modified in main
memory, either an invalidate-TLB or Invalidate-TLB-by-entry operation must
be used to remove any cached copies of the level one descriptor. This is
required regardless of the type of level one descriptor (section, level two
page reference, or fault).
If any of the subpage permissions for a given page are different, each of the
subpages are treated separately. To invalidate all entries associated with a
page with subpage permissions, four MVA-based invalidate operations are
required — one for each subpage.
Caches and write buffer
The ARM926EJ-S processor includes an instruction cache (ICache), data cache
(DCache), and write buffer. The size of the caches can be from 4 KB to 128 KB, in
power of two increments.
Cache features
The caches are virtual index, virtual tag, addressed using the modified
virtual address (MVA). This avoids cache cleaning and/or invalidating on
context switch.
The caches are four-way set associative, with a cache line length of eight
words per line (32 bytes per line), and with two dirty bits in the DCache.
The DCache supports write-through and write-back (copyback) cache
operations, selected by memory region using the C and B bits in the MMU
translation tables.
The caches support allocate on read-miss. The caches perform critical-word
first cache refilling.
The caches use pseudo-random or round-robin replacement, selected by the
RR bit in R1: Control register.
Cache lockdown registers enable control over which cache ways are used
for allocation on a linefill, providing a mechanism for both lockdown and
controlling cache pollution.