Digi NS9750 - Manual (Page 105)

w w w . d i g i e m b e d d e d . c o m 8 1
W o r k i n g w i t h t h e C P U
All CP15 MMU registers, except R8: TLB Operations, contain state that can be read
using
MRC
instructions, and can be written using
MCR
instructions. Registers R5 (Fault
Status) and R6 (Fault Address) are also written by the MMU during an abort.
Writing to R8: TLB Operations causes the MMU to perform a TLB operation, to
manipulate TLB entries. This register is write-only.
Address translation
The virtual address (VA) generated by the CPU core is converted to a modified virtual
address (MVA) by the FCSE (fast context switch extension) using the value held in
CP15 R13: Process ID register. The MMU translates MVAs into physical addresses to
access external memory, and also performs access permission checking.
The MMU table-walking hardware adds entries to the TLB. The translation
information that comprises both the address translation data and the access
permission data resides in a translation table located in physical memory. The MMU
provides the logic for automatically traversing this translation table and loading
entries into the TLB.
The number of stages in the hardware table walking and permission checking process
is one or two. depending on whether the address is marked as a section-mapped
access or a page-mapped access.
There are three sizes of page-mapped accesses and one size of section-mapped
access. Page-mapped accesses are for large pages, small pages, and tiny pages.
R8: TLB Operations
register [31:0] Performs TLB maintenance operations. These are either
invalidating all the (unpreserved) entries in the TLB, or
invalidating a specific entry.
R10: TLB Lockdown
register [28:26] and 0 Enables specific page table entries to be locked into the TLB.
Locking entries in the TLB guarantees that accesses to the
locked page or section can proceed without incurring the time
penalty of a TLB miss. This enables the execution latency for
time-critical pieces of code, such as interrupt handlers, to be
minimized.
Register Bits Description
Table 31: MMU program-accessible CP15 registers