Digi NS9750 - Manual (Page 37)

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Hardware reset duration is 4 ms for PLL to stabilize. Software duration depends on
speed grade, as shown in Table 1.
The minimum reset pulse width is 10 crystal clocks.
System clock
The system clock is provided to the NS9750 by either a crystal or an external
oscillator. Table 2 shows sample clock frequency settings for each chip speed grade.
If an oscillator is used, it must be connected to the
x1_sys_osc
input (C8 pin) on the
NS9750. If a crystal is used, it must be connected with a circuit such as the one shown
in Figure 4.
Speed grade CPU clock cycles Duration
200 MHz 128 640 ns
162 MHz 128 790 ns
125 MHz 128 1024 ns
Table 1: Software reset duration
Speed cpu_clk hclk (main bus) bbus_clk
200 MHz 200 (199.0656) 99.5328 49.7664
162 MHz 162.2016 81.1008 40.5504
125 MHz 125.3376 62.6688 31.3344
Table 2: Sample clock frequency settings with 29.4912 MHz crystal