Digi NS9750 - Manual (Page 314)

S y s t e m c o n f i g u r a t i o n r e g i s t e r s
2 9 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Interrupt Status Raw
Address: A090 016C
The Interrupt Status Raw register shows all current interrupt requests.
Register bit assignment
Bits Access Mnemonic Reset Description
D31:00 R ISRAW 0x0 Interrupt status raw
Provides the status of all active, enabled, and disabled
interrupt request levels, where bit 0 is for the interrupt
assigned to level 0, bit 1 is for the interrupt assigned to
level 1, and so on through bit 31 for the interrupt assigned
to level 31.
Table 181: Interrupt Status Raw register
13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30
Interrupt status raw (ISRAW)
Interrupt status raw (ISRAW)