Digi NS9750 - Manual (Page 697)

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ECP mode
ECP (extended capability port) mode provides a high performance bi-directional
communication path between the host and the peripheral. The ECP protocol provides
two cycle types in both the forward and reverse directions: data cycles and command
cycles.
Two types of command cycles are supported by the IEEE peripheral: run length count
and channel address. The transfer direction is controlled by the host until a
ReverseRequest
signal is issued by the host. The peripheral can set the
PeriphRequest
signal
low to indicate that reverse data is available.
Run_Length_Encoding (RLE) data compression enables real time data compression
that can achieve ratios up to 64:1. NS9750 uses RLE decoding to enable large raster
images with large strings of identical data to be transferred to system memory.
Forward transfer cycles
Be advised:
In forward ECP mode, the
PeriphAck
signal indicates to the host the
ability of the peripheral to accept data. At event #6 of the negotiation
process, the NS9750 indicates to the host that it cannot accept data
and holds its
PeriphAck
signal high for approximately 1200ns.
To differentiate the data cycles from the command cycles, the host sets the HostAck
signal at the beginning of the cycle. When HostAck is asserted low, a command cycle
is occurring and the data represents either an RLE count or a channel address. Bit 7 of
the data byte indicates what is represented:
If bit 7is 0, the data is an RLE count and (
bits[6:0] + 1
) versions of the
subsequent byte are placed into the appropriate forward FIFO based on the
value of HostAck while it is being transferred.
If bit 7 is 1, the data is a channel address (0–127), and bits [6:0] are written
into the Forward Address register ("Forward Address register" on page 703).
Figure 99 shows a data cycle followed by a command cycle.