Digi NS9750 User Manual
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A b o u t N S 9 7 5 0
Internal or external clock support, digital PLL for RX clock extraction
4 receive-side data match detectors
2 dedicated DMA channels per module, 8 channels total
32 byte TX FIFO and 32 byte RX FIFO per module
I
2
C port
I
2
C v.1.0 configurable to master or slave mode
Bit rates: fast (400 kHz) or normal (100 kHz) with clock stretching
7-bit and 10-bit address modes
Supports I
2
C bus arbitration
1284 parallel peripheral port
All standard modes: ECP, byte, nibble, compatibility (also known as SPP or
“Centronix”)
RLE (run length encoding) decoding of compressed data in ECP mode
Operating clock from 100 kHz to 2 MHz
High performance multiple-master/distributed DMA system
Intelligent bus bandwidth allocation (patent pending)
System bus and peripheral bus
System bus
Every system bus peripheral is a bus master with a dedicated DMA engine
Peripheral bus
One 13-channel DMA engine supports USB device
–
2 DMA channels support control endpoint
–
11 DMA channels support 11 endpoints
One 12-channel DMA engine supports:
–
4 serial modules (8 DMA channels)
–
1284 parallel port (4 DMA channels)
All DMA channels support fly-by mode
External peripheral
One 2-channel DMA engine supports external peripheral connected to
memory bus