Digi NS9750 - Manual (Page 436)

A b o u t t h e P C I - t o - A H B B r i d g e
4 1 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
D23:16 R/W BUS_NUMBER 0x00 Target PCI bus number
Bus 0. Considered a local bus, so a Type 0
configuration is performed.
All other bus numbers. Result in a Type 1
cycle that targets an external bus (that is, a
bus on the other side of a PCI-to-PCI
bridge).
D15:11 R/W DEVICE_NUMBER 0x00 Target PCI device number
For Type 0 cycles, the bridge uses this field to
determine which bit of AD[31:11] is the only bit
set during the configuration cycle on the PCI bus.
This will be the bit that is connected to the IDSEL
input of the device assigned to this device
number.
Note: This value must be 0 for internal
registers.
Example:
If DEVICE_NUMBER = 0x01,
AD[31:11] = 0x000002
D10:08 R/W FUNCTION_NUMBER 0x0 Target function number within PCI device
This value is 0x0 for all accesses to bridge
registers. This value is mapped to AD[10:08]
during the configuration cycle.
D07:02 R/W REGISTER_NUMBER 0x00 Target register address within the PCI
32-bit register, whose value is mapped to
AD[07:02] during the configuration cycle.
Example:
If the PCI Vendor ID register is being accessed,
the REGISTER_NUMBER will be 0x00. (See
Table 254, “PCI/bridge configuration registers,”
on page 413 for more information.)
D01:00 R/W TYPE 0x0 Type field
The value in this field must be 00 for Type 0
cycles and 01 for Type 1 cycles.
This value is mapped to AD[01:00] during the
configuration cycle.
Bits Access Mnemonic Reset Description
Table 253: CONFIG_ADDR register