Table 425: hccommandstatus register – Digi NS9750 User Manual
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U S B C o n t r o l l e r M o d u l e
The host controller uses the HcCommandStatus register to receive commands issued
by the host controller driver, as well as to reflect the current status of the host
controller. The HcCommandStatus register appears to the host controller driver as a
write to set register. The host controller must ensure that bits written as 1 become
set in the register while bits written as 0 remain unchanged in the register. The host
controller driver can issue multiple distinct commands to the host controller without
concern for corrupting previously-issued commands. The host controller driver has
normal read access to all bits. The host controller driver has normal read access to all
bits.
Register bit description
Bits
Access
Mnemonic
Reset
Description
D31:18
N/A
Reserved
N/A
N/A
D17:16
R
SOC
00b
SchedulingOverrunCount
Indicates the number of frames with which the host
controller has found a scheduling overrun error. A
scheduling overrun error occurs when the periodic list
does not complete before EOF. When a scheduling
overrun error is found, the host controller increments the
counter and sets the Scheduling Overrun field in the
HcInterruptStatus register (see "HcInterruptStatus
register," beginning on page 733).
This field initializes to 00b and wraps around at 11b.
This field is incremented on each scheduling overrun
error, even if the SchedulingOverrun field in the
HcInterruptStatus register has already been set. The host
controller driver uses this field to monitor any persistent
scheduling problems.
Table 425: HcCommandStatus register
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
OCR
BLF
SOC
CLF
HCR