Digi NS9750 User Manual
Page 220
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D y n a m i c m e m o r y c o n t r o l l e r
1 9 6
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Table 130 shows the outputs from the memory controller and the corresponding
inputs to the 64M SDRAM (8Mx*, pins 13 and 14 used as bank selects).
4
4
13
5
3
3
12
4
2
2
11
3
1
1
10
2
0
0
9
**
Output address
(
ADDROUT
)
Memory device
connections
AHB address to row
address
AHB address to
column address
14
BA1
23
23
13
BA0
22
22
12
-
-
-
11
11
21
-
10
10/AP
20
AP
9
9
19
-
8
8
18
9
7
7
17
8
6
6
16
7
5
5
15
6
4
4
14
5
3
3
13
4
2
2
12
3
1
1
11
2
0
0
10
**
Table 130: Address mapping for 64M SDRAM (8Mx8, BRC)
Output address
(
ADDROUT
)
Memory device
connections
AHB address to row
address
AHB address to
column address
Table 129: Address mapping for 64M SDRAM (4Mx16, BRC)
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