Digi NS9750 - Manual (Page 361)

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E t h e r n e t C o m m u n i c a t i o n M o d u l e
Ethernet Control and Status registers
Table 205 shows the address for each Ethernet controller register. All configuration
registers must be accessed as 32-bit words and as single accesses only. Bursting is not
allowed.
Address Register Description
A060 0000 EGCR1 Ethernet General Control Register #1
A060 0004 EGCR2 Ethernet General Control Register #2
A060 0008 EGSR Ethernet General Status register
A060 000C–A060 0014 Reserved
A060 0018 ETSR Ethernet Transmit Status register
A060 001C ERSR Ethernet Receive Status register
A060 0400 MAC1 MAC Configuration Register #1
A060 0404 MAC2 MAC Configuration Register #2
A060 0408 IPGT Back-to-Back Inter-Packet-Gap register
A060 040C IPGR Non-Back-to-Back Inter-Packet-Gap register
A060 0410 CLRT Collision Window/Retry register
A060 0414 MAXF Maximum Frame register
A060 0418 SUPP PHY Support register
A060 041C Reserved
A060 0420 MCFG MII Management Configuration register
A060 0424 MCMD MII Management Command register
A060 0428 MADR MII Management Address register
A060 042C MWTD MII Management Write Data register
A060 0430 MRDD MII Management Read Data register
A060 0434 MIND MII Management Indicators register
A060 0440 SA1 Station Address Register #1
A060 0444 SA2 Station Address Register #2
Table 205: Ethernet Control and Status register map