Digi NS9750 User Manual

Page 284

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S y s t e m b u s a r b i t e r

2 6 0

N S 9 7 5 0 H a r d w a r e R e f e r e n c e

The available bandwidth per master is calculated using this formula:

Bandwidth per master:

= [(100MHz/2) / (16 clock cycles per access x 6 masters)] x 32 bytes

= 16.667 Mbytes/master

If the LCD is configured for two arbiter channel slots, then, there are 33.334 Mbytes
available, which is greater than the 25 Mbytes required. Each of the other masters
have 16.667 Mbytes available, which is more than enough to meet their
requirements.

Note:

When assigning two arbiter channel slots to a master, the slot assignments
should be spaced equally.

The AHB arbiter will be programmed as follows:

BRC0[31:24]

= 8’b1_0_00_0000

channel enabled, 100%, ARM926EJ-S

BRC0[23:16]

= 8’b1_0_00_0001

channel enabled, 100%, Ethernet Rx

BRC0[15:8]

= 8’b1_0_00_0000

channel enabled, 100%, ARM926EJ-S

BRC0[7:0]

= 8’b1_0_00_0010

channel enabled, 100%, Ethernet Tx

BRC1[31:24]

= 8’b1_0_00_0000

channel enabled, 100%, ARM926EJ-S

BRC1[23:16]

= 8’b1_0_00_0110

channel enabled, 100%, LCD first slot

BRC1[15:8]

= 8’b1_0_00_0000

channel enabled, 100%, ARM926EJ-S

BRC1[7:0]

= 8’b1_0_00_0100

channel enabled, 100%, PCI

BRC2[31:24]

= 8’b1_0_00_0000

channel enabled, 100%, ARM926EJ-S

BRC2[23:16]

= 8’b1_0_00_0101

channel enabled, 100%, BBus

BRC2[15:8]

= 8’b1_0_00_0000

channel enabled, 100%, ARM926EJ-S

BRC2[7:0]

= 8’b1_0_00_0110

channel enabled, 100%, LCD second slot

BRC3[31:24]

= 8’b0_0_00_0000

channel disabled

BRC3[23:16]

= 8’b0_0_00_0000

channel disabled

BRC3[15:8]

= 8’b0_0_00_0000

channel disabled

BRC[7:0]

= 8’b0_0_00_0000

channel disabled

Note that the BBus requires 4 Mbytes but has been allocated 16.667 Mbytes. The BBus
bandwidth can be reduced using the bandwidth reduction field (in the BRC registers).
To reduce the available bandwidth by 25% to 4.167 Mbytes, for example, the 2-bit
field can be set to

2’b11

. This restricts the BBus master when the system is fully

loaded. The new configuration for BBus is:

BRC2[23:16]

= 8’b1_0_11_0101

channel enabled, 25%, BBus

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