Digi NS9750 - Manual (Page 762)

U S B h o s t b l o c k r e g i s t e r s
7 3 8 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Register bit assignment
Bits Access Mnemonic Reset Description
D31 R/W MIE 0b Master interrupt enable
0 Ignored by the host controller.
1 Disables interrupt generation due to events specified
in other bits in this register.
This field is set after a hardware or software reset.
D30 R/W OC 0b Ownership change
0 Ignore
1 Disable interrupt generation due to ownership
change.
D29:07 N/A Reserved N/A N/A
D06 R/W RHSC 0b Root hub status change
0 Ignore
1 Disable interrupt generation due to root hub status
change.
D05 R/W FNO 0b Frame number overflow
0 Ignore
1 Disable interrupt generation due to frame number
overflow.
D04 R/W UE 0b Unrecoverable error
0 Ignore
1 Disable interrupt generation due to unrecoverable
error.
D03 R/W RD 0b Resume detect
0 Ignore
1 Disable interrupt generation due to resume detect.
D02 R/W SF 0b Start of frame
0 Ignore
1 Disable interrupt generation due to start of frame.
D01 R/W WDH 0b HcDoneHead writeback
0 Ignore
1 Disable interrupt generation due to HcDoneHead
writeback.
Table 428: HcInterruptDisable register