Digi NS9750 - Manual (Page 445)

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P C I - t o - A H B B r i d g e
Address Offset Register Description
0xA030 0000 PARBCFG PCI Arbiter Configuration
0xA030 0004 PARBINT PCI Arbiter Interrupt Status
0xA030 0008 PARBINTEN PCI Arbiter Interrupt Enable
0xA030 000C PMISC PCI Miscellaneous Support
0xA030 0010 PCFG0 PCI Configuration 0
0xA030 0014 PCFG1 PCI Configuration 1
0xA030 0018 PCFG2 PCI Configuration 2
0xA030 001C PCFG3 PCI Configuration 3
0xA030 0020 PAHBCFG PCI Bridge Configuration
0xA030 0024 PAHBERR PCI Bridge AHB Error Address
0xA030 0028 PCIERR PCI Bridge PCI Error Address
0xA030 002C PINTR PCI Bridge Interrupt Status
0xA030 0030 PINTEN PCI Bridge Interrupt Enable
0xA030 0034 PALTMEM0 PCI Bridge AHB to PCI Memory Address Translate 0
0xA030 0038 PALTMEM1 PCI Bridge AHB to PCI Memory Address Translate 1
0xA030 003C PALTIO PCI Bridge AHB to PCI IO Address Translate
0xA030 0040 PMALT0 PCI Bridge PCI to AHB Memory Address Translate 0
0xA030 0044 PMALT1 PCI Bridge PCI to AHB Memory Address Translate 1
0xA030 0048 PALTCTL PCI Bridge Address Translation Control
0xA030 004C CMISC CardBus Miscellaneous Support
0xA030 004C–0xA030 0FFC Reserved (all read accesses return 0x0 value)
0xA030 1000 CSKTEV CardBus Socket Event
0xA030 1004 CSKTMSK CardBus Socket Mask
0xA030 1008 CSKTPST CardBus Socket Present State
0xA030 100C CSKTFEV CardBus Socket Force Event
0xA030 1010 CSKTCTL CardBus Socket Control
Table 259: PCI arbiter register map