Lcdtiming0 – Digi NS9750 User Manual
Page 604
R e g i s t e r s
5 8 0
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
LCDTiming0
Address: A080 0000
The LCDTiming0 register controls the horizontal axis panel, which includes:
Horizontal synchronization pulse width (HSW)
Horizontal front porch (HFP) period
Horizontal back porch (HBP) period
Pixels-per-line (PPL)
Register bit assignment
Bits
Access
Mnemonic
Reset
Description
D31:24
R/W
HBP
0x00
Horizontal back porch
Number of
CLCP
periods between the negation of
CLLP
and the start of active data. Program this field
with value minus 1.
HBP specifies the number of pixel clock periods
inserted at the beginning of each line or row of pixels.
HBP can generate a delay of 1 to 256 pixel clock
cycles.
D23:16
R/W
HFP
0x00
Horizontal front porch
Number of
CLCP
periods between the end of active
data and the assertion of
CLLP
. Program this field with
value minus 1.
HFP sets the number of pixel clock periods at the end
of each line or row of pixels, before
CLLP
is asserted.
HFP can generate a period of 1 to 256 pixel clock
cycles.
Table 350: LCDTiming0 register
HBP
PPL
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
HSW
HFP
Reserved