Digi NS9750 - Manual (Page 492)

B B u s b r i d g e f u n c t i o n s
4 6 8 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
BBus bridge functions
The Digi BBus is a low-speed secondary bus that operates at half the AHB clock
frequency. The BBus interface houses the slower serial interfaces for USB, IEEE 1284,
SPI, and UART, as well as dedicated BBus DMA control, to offload some of the
bandwidth demands of the primary AHB bus. The BBus bridge controls the flow of
data between the AHB and BBus interfaces.
The BBus bridge provides these functions:
BBus arbitration and multiplexing. The USB and DMA peripheral, in
addition to the BBus bridge, can be BBus masters. All BBus peripherals
contain a slave interface.
Two-channel DMA controller. The DMA controller performs memory-to-
memory transfers across the AHB bus, allowing DMA transfers from an
external peripheral to external memory or from external memory to an
external peripheral.
System boot engine that fetches data from an external SPI-EEPROM and
writes it to an external SDRAM. The boot engine configures the memory
controller accordingly, before fetching the contents of the EEPROM. While a
serial boot operation takes place, the CPU is held in reset.