Digi NS9750 User Manual
Page 355
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E t h e r n e t C o m m u n i c a t i o n M o d u l e
The slave also generates an AHB
ERROR
if the address is not aligned on a 32-bit
boundary, and the
misaligned bus address response mode
is set in the Miscellaneous System
Configuration register (see "Miscellaneous System Configuration and Status register,"
beginning on page 296). In addition, accesses to non-existent addresses result in an
AHB
ERROR
response.
Interrupts
Separate RX and TX interrupts are provided back to the system. Table 203 shows all
interrupt sources and the interrupts to which they are assigned.
Interrupt condition
Description
Interrupt
RX data FIFO overflow
RX data FIFO overflowed.
For proper operation, reset the receive packet processor using the
ERX bit in the Ethernet General Control Register #1 when this
condition occurs.
RX
RX status FIFO overflow
RX status overflowed.
RX
Receive buffer closed
I bit set in receive buffer descriptor and buffer closed.
RX
Receive complete (Pool
A)
Complete receive frame stored in pool A of system memory.
RX
Receive complete (Pool
B)
Complete receive frame stored in pool B of system memory.
RX
Receive complete (Pool
C)
Complete receive frame stored in pool C of system memory.
RX
Receive complete (Pool
D)
Complete receive frame stored in pool D of system memory.
RX
No receive buffers
No buffer is available for this frame because all 4 buffer rings are
disabled, full, or no available buffer is big enough for the frame.
RX
Receive buffers full
No buffer is available for this frame because all 4 buffers are
disabled or full.
RX
RX buffer ready
Frame available in
RX_FIFO
. (Used for diagnostics.)
RX
Statistics counter
overflow
One of the statistics counters has overflowed. Individual counters
can be masked using the CAM1 and CAM2 registers.
TX
Transmit buffer closed
I bit set in Transmit buffer descriptor and buffer closed.
TX
Table 203: Ethernet interrupt conditions