Bbus control logic – Digi NS9750 User Manual
Page 496
B B u s c o n t r o l l o g i c
4 7 2
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
BBus control logic
BBus control logic consists of a round-robin arbiter to select a new master, the
multiplexing logic to provide the new master’s signals to the BBus slaves, and address
decoding to select the target BBus slave.
BBus bridge masters and slaves
BBus bridge arbitration allows each bus master to control the bus in a round-robin
manner. If a bus master does not require the bus resources when its turn comes
around, that bus master is skipped until the next round-robin slot. Each potential bus
master presents the bus with request and attribute signals. Once the bus grants
mastership, the targeted device is selected.
Note:
The CPU always is granted mastership when requested, because its
transactions are time-sensitive and completed within 4 BBus clock cycles.
When the CPU requests use of the bus, it must wait until the current
transaction finishes. The CPU then takes mastership and performs its
transaction, before the next BBus master with a pending request. When
the CPU transaction is finished, the bus grants mastership to the
appropriate requesting BBus master.
Table 287 shows the BBus bus master and slave modules.
Module
Master
Slave
BBus bridge
Y
Y
BBus DMA
Y
Y
SER
Y
I2C
Y
1284
Y
USB dev
Y
USB DMA
Y
Y
USB host
Y
Y
Table 287: BBus master and slave modules