71 l_dflipflop_2, 71 l_dflipflop_2 4, L_dflipflop_2 – Lenze 8400 HighLine User Manual

Page 1334: 17 function library

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17

Function library

17.1

Function blocks

1334

Lenze · 8400 HighLine · Referenzhandbuch · DMS 10.0 EN · 06/2014 · TD05/TD14

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If the bClr input = TRUE:

• Due to the priority bClr > bClk, bD the bOut output signal can be set any time to the FALSE status

by the bClr input signal = TRUE.

• The output signal is kept in this status independent of the other input signals.

17.1.71

L_DFlipFlop_2

The FB saves binary signals (DFlipFlop) in a clock-controlled way.

Inputs

Outputs

Identifier

Data type

Information/possible settings

bD

BOOL

Data input

bClk

BOOL

Clock input

• Only FALSE/TRUE edges are evaluated

bClr

BOOL

Reset input

TRUE

• The bOut output is set to FALSE.

• The bNegOut output is set to TRUE.

Identifier

Data type

Value/meaning

bOut

BOOL

Output signal

bNegOut

BOOL

Output signal, inverted

For a detailed functional description see

L_DFlipFlop_1

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