Freescale Semiconductor MPC8260 - Manual (Page 1015)

ATM Controller and AAL0, AAL1, and AAL5
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 30-95
samples a new SRTS and stores it internally. The SRTS is a sample of a 4-bit counter with a 2.43-MHz
reference clock (for E1/T1) synchronized with the network clock.
The PowerQUICC II supports clock recovery using an external SRTS PLL. If SRTS recovery is enabled
(RCT[SRT]=1), the PowerQUICC II tracks the SRTS from four incoming cells whose SN field equals 1,
3, 5, and 7 and writes the result to external SRTS logic, as shown in
Figure 30-65 .
Figure 30-65. AAL1 CES SRTS Clock Recovery Using External Logic
On every eighth cell, the PowerQUICC II writes a new SRTS code to the external logic using the bus
selected in RCT[BIB]. The CP writes the SRTS code using a DMA write cycle of 1-byte data size. Each
AAL1 CES channel can be programmed to select one of 16 addresses available for writing the SRTS result.
The SRTS code is written to the least-significant nibble of that address (SRTS[0]=lsb, SRTS[3]=msb). The
SRTS is synchronized with the sequence count cycle—SRTS[3] is read from the cell with SN = 1 and
SRTS[0] is read from the cell with SN = 7. The SRTS PLL makes periodic clock adjustments based on the
difference between a locally generated SRTS and a remotely generated SRTS retrieved every eight
received cells.
30.16 Configuring the ATM Controller for Maximum CPM Performance
The following sections recommend ATM controller configurations to maximize CPM performance.
30.16.1 Using Transmit Internal Rate Mode
When the total transmit rate is less than the PHY rate, use the transmit internal rate mode and configure
the internal rate clock to the maximum bit rate required. (See
30.2.1.5, “Transmit External Rate and
Internal Rate Modes.” ) The PHY then automatically fills the unused bandwidth with idle cells, not the
ATM controller. If the internal rate mode is not used, CPM performance is consumed generating the idle
cell payload and using the scheduling algorithm to fill the unused bandwidth at the higher PHY rate.
p = 4 bit
1/64
155.52 MHz
2.43 MHz (E1/T1)
Latch
fs Counter
divided by N
(N=3008 bits = 8 SAR PDU)
SRTS
External SRTS Logic
SRTS Diff
+
-
VCO
SN=1 SN=3 SN=5 SN=7
DMA writes new SRTS code
Latch
counter