Freescale Semiconductor MPC8260 - Manual (Page 791)

SCC Ethernet Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 25-7
generate writes to the CAM for address recognition. In addition, the RENA signal supplied from the SIA
can be used to abort the comparison if a collision occurs on the receive frame.
After the comparison, the CAM control logic asserts the receive reject signal (REJECT), if the current
receive frame is rejected. The PowerQUICC II’s Ethernet controller then immediately stops writing data
to system memory and reuses the buffer(s) for the next frame. If the CAM accepts the frame, the CAM
control logic does nothing (REJECT is not asserted). However, if REJECT is asserted, it must be done
prior to the end of the receive frame.
NOTE
The bus atomicity mechanism for CAM accesses may not function correctly
when the CPM performs a DMA access to an external CAM device. This
only impacts systems in which multiple CPMs will access the CAM.
25.7 SCC Ethernet Parameter RAM
For Ethernet mode, the protocol-specific area of the SCC parameter RAM is mapped as in Table 25-1 .
Table 25-1. SCC Ethernet Parameter RAM Memory Map
Offset 1 Name Width Description
0x30 C_PRES Word Preset CRC. For the 32-bit CRC-CCITT, initialize to 0xFFFFFFFF.
0x34 C_MASK Word Constant mask for CRC. For the 32-bit CRC-CCITT, initialized to 0xDEBB20E3.
0x38 CRCEC Word CRC error, alignment error, and discard frame counters. The CPM maintains
these 32-bit (modulo 2
32
) counters that can be initialized while the channel is
disabled. CRCEC is incremented for each received frame with a CRC error, not
including frames not addressed to the controller, frames received in the
out-of-buffers condition, frames with overrun errors, or frames with alignment
errors. ALEC is incremented for frames received with dribbling bits, but does not
include frames not addressed to the controller, frames received in the
out-of-buffers condition, or frames with overrun errors. DISFC is incremented for
frames discarded because of the out-of-buffers condition or an overrun error. The
CRC does not have to be correct for DISFC to be incremented.
0x3C ALEC
0x40 DISFC
0x44 PADS Hword Short frame PAD character. Write the pad character pattern to be sent when short
frame padding is implemented into PADS. The pattern may be of any value, but
both the high and low bytes should be the same.
0x46 RET_LIM Hword Retry limit. Number of retries (typically 15 decimal) that can be made to send a
frame. An interrupt can be generated if the limit is reached.
0x48 RET_CNT Hword Retry limit counter. Temporary down-counter for counting retries.
0x4A MFLR Hword Maximum frame length register (Typically 1518 decimal). The Ethernet controller
checks the length of an incoming Ethernet frame against this limit. If it is
exceeded, the rest of the frame is discarded and LG is set in the last BD of that
frame. The controller reports frame status and length in the last BD. MFLR is
defined as all in-frame bytes between the start frame delimiter and the end of the
frame.