Freescale Semiconductor MPC8260 - Manual (Page 266)

60x Signals
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
7-10 Freescale Semiconductor
State Meaning Asserted—Indicates that a 60x bus slave is terminating the address tenure. On the
cycle following the assertion of AACK, the bus master releases the address tenure
related signals to the high-impedance state and samples ARTRY.
Negated—Indicates that the address tenure must remain active and the address
tenure related signals driven.
Timing Comments Assertion—Occurs during the 60x bus slave access, at least two clocks after TS.
Negation—Occurs one clock after assertion.
7.2.5.2 Address Retry (ARTRY)
The address retry (ARTRY) signal is both an input and output signal on the PowerQUICC II.
7.2.5.2.1 Address Retry (ARTRY)—Output
Following are the state meaning and timing comments for ARTRY as an output signal.
State Meaning Asserted—Indicates that the PowerQUICC II detects a condition in which an
address tenure must be retried. If the PowerQUICC II processor needs to update
memory as a result of snoop that caused the retry, the PowerQUICC II asserts BR
the second cycle after AACK if ARTRY is asserted.
High Impedance—Indicates that the PowerQUICC II does not need the address
tenure to be retried.
Timing Comments Assertion—Asserted the third bus cycle following the assertion of TS if a retry is
required.
Negation—Occurs the second bus cycle after the assertion of AACK. Since this
signal may be simultaneously driven by multiple devices, it negates in a unique
fashion. First the buffer goes to high impedance for a minimum of one-half
processor cycle (dependent on the clock mode), then it is driven negated for one
bus cycle before returning to high impedance.
7.2.5.2.2 Address Retry (ARTRY)—Input
Following are the state meaning and timing comments for the ARTRY input.
State Meaning Asserted—If the PowerQUICC II is the address bus master, ARTRY indicates that
the PowerQUICC II must retry the preceding address tenure and immediately
negate BR (if asserted). If the associated data tenure has started, the PowerQUICC
II also aborts the data tenure immediately even if the burst data has been received.
If the PowerQUICC II is not the address bus master, this input indicates that the
PowerQUICC II should negate BR for one bus clock cycle immediately after
external device asserts ARTRY to permit a copy-back operation to main memory.
Note that the subsequent address presented on the address bus may not be the one
that generated the assertion of ARTRY.
Negated/High Impedance—Indicates that the PowerQUICC II does not need to
retry the last address tenure.