Freescale Semiconductor MPC8260 - Manual (Page 1191)

ATM Transmission Convergence Layer
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 34-13
34.4.3.6 Filtered Cell Counter [1–8] (TC_FCC x)
This cell counter is updated whenever an idle/unassigned cell is filtered (discarded). If cell filters are not
enabled (TCMODE[CF] is cleared), this counter is not updated.
34.4.4 Programming FCC2
FCC2 is designed to work with the TC blocks. The TC blocks are located on fixed addresses on the
UTOPIA bus internally. FCC2 should be programmed to work with the TC blocks as if the TC blocks are
external PHYs located on the lowest eight (or fewer) addresses.
34.4.5 Programming and Operating the TC Layer
34.4.5.1 Receive
The TC layer receive operation is enabled by setting TCMODEx[RXEN].
The host software polls the CD bits of each enabled TC layer block to see that its receive cell delineation
state machines are synchronized. For each TC layer block that is synchronized, the host clears
TCERx[CDT]. Once all the enabled TC layer blocks are synchronized, the host terminates its initialization
routine, and the system starts normal operation.
Once a TC block gets out of synchronization, the corresponding TCGSR[CD] is cleared. This change then
causes a TCER[CDT] interrupt to the host (if enabled in the mask register—TCMRx).
On the receive path, the TC layer receives the bit stream via the SI and does the following:
1. Attempts to gain synchronization on the ATM cell boundaries by checking each byte against the
HEC calculated on the preceding 32 bits (ATM cell header candidate).
2. Once synchronized:
— Performs the descrambling function on the cell payload (if enabled)
— Performs the coset function on the HEC (if enabled)
— Checks for HEC errors and corrects single HEC errors when found (again, if enabled). Cells
containing multi-bit header errors (at least 2 errors) are discarded. Idle and unassigned cells are
filtered (discarded) when detected (if the filters are enabled).
Once an ATM cell’s processing is complete, it is passed to the TC layer receive FIFO and the internal TC
layer cell counters are updated. The cell is passed from the TC layer receive FIFO via the internal UTOPIA
interface to the FCC2 receive FIFO.
An overrun condition occurs when the TC layer receive FIFO is full and the FCC is unable to read a cell
from it (via the internal UTOPIA interface) before another valid cell is received. The incoming cell is
discarded and TCER[OR] interrupt is sent to the host (if enabled in the mask register—TCMRx).
34.4.5.2 Transmit
The TC layer transmit operation is enabled by setting TCMODEx[TXEN].