Freescale Semiconductor MPC8260 - Manual (Page 318)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
9-12 Freescale Semiconductor
When the PCI bridge as a target needs to suspend a transaction, it asserts STOP. Once asserted, STOP
remains asserted until FRAME is negated. Depending on the circumstances, data may or may not be
transferred during the request for termination. If TRDY and IRDY are asserted during the assertion of
STOP, data is transferred. This type of target-initiated termination is called a ‘disconnect B,’ shown in
Figure 9-7 . If TRDY is asserted when STOP is asserted but IRDY is not, TRDY must remain asserted until
IRDY is asserted and the data is transferred. This is called a “disconnect A” target-initiated termination,
also shown in
Figure 9-7 . However, if TRDY is negated when STOP is asserted, no more data is
transferred, and the initiator therefore does not have to wait for a final data transfer (see the ‘retry’ diagram
in
Figure 9-7 ).
Figure 9-7. Target-Initiated Terminations
Note that when an initiator is terminated by STOP, it must negate its REQx signal for a minimum of two
PCI clocks (of which one clock is needed for the bus to return to the idle state). If the initiator intends to
complete the transaction, it should reassert its REQx immediately following the two clocks or potential
starvation may occur. If the initiator does not intend to complete the transaction, it can assert REQx
whenever it needs to use the PCI bus again.
The PCI bridge terminates a transaction in the following cases:
• Eight PCI clock cycles have elapsed between data phases. This is a ‘latency disconnect’ (see
Figure 9-7 ).
PCI_CLK
FRAME
IRDY
DEVSEL
TRDY
STOP
Disconnect A Disconnect B Retry
PCI_CLK
FRAME
IRDY
DEVSEL
TRDY
STOP
Latency disconnect
PCI_CLK
FRAME
IRDY
DEVSEL
TRDY
STOP
Target abort