Freescale Semiconductor MPC8260 - Manual (Page 419)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 11-1
Chapter 11
Memory Controller
The memory controller is responsible for controlling a maximum of twelve memory banks sharing a high
performance SDRAM machine, a general-purpose chip-select machine (GPCM), and three
user-programmable machines (UPMs). It supports a glueless interface to synchronous DRAM (SDRAM),
SRAM, EPROM, flash EPROM, burstable RAM, regular DRAM devices, extended data output DRAM
devices, and other peripherals. This flexible memory controller allows the implementation of memory
systems with very specific timing requirements.
• The SDRAM machine provides an interface to synchronous DRAMs, using SDRAM pipelining,
bank interleaving, and back-to-back page mode to achieve the highest performance.
• The GPCM provides interfacing for simpler, lower-performance memory resources and
memory-mapped devices. The GPCM has inherently lower performance because it does not
support bursting. For this reason, GPCM-controlled banks are used primarily for boot-loading and
access to low-performance memory-mapped peripherals.
• The UPM supports address multiplexing of the external bus, refresh timers, and generation of
programmable control signals for row address and column address strobes to allow for a glueless
interface to DRAMs, burstable SRAMs, and almost any other kind of peripheral. The refresh
timers allow refresh cycles to be initiated. The UPM can be used to generate different timing
patterns for the control signals that govern a memory device. These patterns define how the
external control signals behave during a read, write, burst-read, or burst- write access request.
Refresh timers are also available to periodically generate user-defined refresh cycles.
Unless stated otherwise, this chapter describes the 60x bus memory controller. The local bus memory
controller provides the same functionality as the 60x bus memory controller except 64-bit port size, ECC,
and external master support.
The PowerQUICC II supports the following new features as compared to the MPC860 and MPC850.
• The synchronous DRAM machine enables back-to-back memory read or write operations using
page mode, pipelined operation and bank interleaving for high-performance systems.
• The memory controller supports the local bus and the 60x bus in parallel. The 60x bus and the local
bus share twelve memory banks as well as two SDRAM machines, three user-programmable
machines (UPMs) and GPCMs.
• The memory controller supports atomic operation.
• The memory controller supports read-modify-write (RMW) data parity check.
• The memory controller supports ECC data check and correction.
• Two data buffer controls (one for the local bus).
• ECC/parity byte select pin, which enables a fast, glueless connection to ECC/RMW-parity devices.