Freescale Semiconductor MPC8260 - Manual (Page 327)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 9-21
completes one more data phase and relinquishes the bus. The master latency timer can be disabled if
needed (see
Section 9.11.2.22, “PCI Bus Function Register” ).
9.10 Address Map
A transaction sent to the PCI bridge from any 60x bus master side falls into one of the following three
cases:
• If the transaction address is within the internal register space of the PowerQUICC II, the
transaction is handled by the PCI bridge internal register logic. (The internal registers are described
in this chapter.)
• If the transaction address is within one of the three outbound PCI translation windows (described
in this chapter), the transaction is sent to the PCI bus with address translation.
• If the transaction address is not within the internal register space and not within a PCI translation
window, the transaction is sent to the PCI bus with no address translation as a PCI memory
transaction to non-prefetchable space.
An address decode flow chart for transactions from the 60x bus masters to the PCI bridge is shown in
Figure 9-11 .
Figure 9-11. Address Decode Flow Chart for 60x Bus Mastered Transactions
Transactions directed to the PowerQUICC II from a PCI bus master are handled as follows:
• If the transaction address is within the internal register space of the PowerQUICC II, the
transaction is either handled by the PCI bridge internal register logic or forwarded to the core side
of the PCI bridge to be handled by the PowerQUICC II internal register logic as appropriate.
Hit PCI
internal registers
?
Hit
Outbound ATU
?
No
Yes
60x bus mastered
Hit
IMMR
?
transaction
(1)
Yes
No
Execute register
access to
PCI interface
internal registers
Hit
PCIBR0/PCIBR1
?
No action
Yes
No
Translate the
address
Issue transaction
with translated
address to PCI
Yes
No
Issue transaction
with un-translated
address to PCI
(1): IMMR+0x10400
≤ addr ≤ IMMR+0x10bff