Freescale Semiconductor MPC8260 - Manual (Page 282)

The 60x Bus
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
8-8 Freescale Semiconductor
with BG INT-asserted (note that BG INT is an internal signal not seen by the user at the pins), which lets
it start an address bus tenure by asserting TS. During the same clock cycle, the external master’s bus
request is asserted to request access to the 60x bus, thereby causing the negation of BG INT internally and
the assertion of BG at the pin. Following PowerQUICC II’s address tenure, the external master takes the
bus and initiates its address transaction. The on-chip arbiter samples BR during the clock cycle in which
AACK is asserted; if BR is not asserted (no pending request), it negates BG and asserts the parked bus
grant (BG_INT in this example).
The master can assert BR and receive a qualified bus grant without subsequently using the bus. It can
negate (cancel) BR before accepting a qualified bus grant. This can occur when a replacement copyback
transaction waiting to be run on the bus is killed by a snoop of another bus master. This can also occur
when the reservation set by a pending stwcx. transaction is cancelled by a snoop of another master. In both
cases, the pending transaction by the processor is cancelled and BR is negated.
Figure 8-4. Address Bus Arbitration with External Bus Master
8.4.2 Address Pipelining
The PowerQUICC II supports one-level address pipelining by asserting AACK to the current bus master
when its data tenure starts and by granting the address bus to the next requesting device before the current
data bus tenure completes. Address pipelining improves data throughput by allowing the memory-control
hardware to decode a new set of address and control signals while the current data transaction finishes.
The PowerQUICC II pipelines data bus operations in strict order with the associated address operations.
Figure 8-5 shows how address pipelining allows address tenures to overlap the associated data tenures.
CLKOUT
BR INT
BG INT PowerQUICC II
BR
BG
ABB
ADDR+ PowerQUICC II External External
TS
AACK
ARTRY